@forumulator wrote:
@cfelton, @martin, @andreprado88, @hgomersall
My final blog is done and here : http://pyleros.blogspot.in/2016/08/gsoc-final-summary-and-development.html. 95% of my project is done, just the command bridge remains, which is honestly, not that big a deal to write, I'm just out of time.I have the timing and flow down to the finest details, so when I do write that, I expect to be able to interface it with rhea cores and test it immediately.
A slight problem is that the VHDL synthesizer is currently not able to infer RAM from the code, and is instead using registers, have to also look into that.
Also, please have a look at https://github.com/forumulator/pyLeros/blob/master/README.md#usage